At ISSCC 2023, SK hynix presented the concept of a 3D NAND flash memory with over 300 layers. Developers are hoping to increase chip throughput from 164 to 194 MB/s.
The number of layers has increased and the step between them has decreased, thus increasing the resistance of the wordline (WL) line connecting the cells in the matrix row. If this growth is not compensated, the speed and energy efficiency will decline.
The cell density will increase from 11.55 Gb / mm2 for 238-layer memory to more than 20 Gb / mm2.
According to the engineers, memory performance might be improved in five ways. This includes speeding up the write, erase, and read processes.
Instead of the previously double DPGM verification, the group members will be divided into four groups, rather than three. The TPGM technique reduces the tPROG parameter, and together with the increased split will shorten cell programming time by about 10%.
The tPROG parameter will be reduced by about 2% by the Unselected String Adaptive Precharge (AUSP) technique.
The WL line's capacitive load will be reduced, resulting in a programmable dummy string (PDS) method. The All Pass Rise (APR) method will result in a decrease in read time (tR) and increases the read time by 2%.
A Plane Level Reread (PLRR) technique may be employed to improve service quality during erasing.
With a simultaneous increase in recording density, 1-Tbit 3D NAND TLC will speed up from 164 MB / s to 194 MB / s.
By the end of the year or early 2024, the first 3D NAND prototypes will be available.