SK hynix presented a presentation at ISSCC 2023, revealing the development of a 300-layer 3D NAND flash memory, which underscores the complexity of enhancing the technical process for the production of multilayer flash memory: from 164 MB / s to 194 MB / s.
The previous record holder is a 238-layer 3D NAND SK hynix. Image source: SK hynix.
The SK hynix engineers are working on two main and most essential areas: to increase the recording density (reduce the cost of storing each bit of data) and increase performance. Both involve an increase in the length of the wordline (WL) line connecting the cells in the matrix row.
Comparison of 238 and 300-layer 3D NANDs
A hypothetical NAND memory chip with over 300 layers will be shown in a slew of papers. The cell density will decrease from 11.55 Gb / mm2 for the current 238-layer memory to more than 20 Gb / mm2.
In the new version, the cells will be divided into four groups, rather than three. This along with an increase in cell breakdown by about 10% will shorten the cell programming time.
The new Adaptive Unselected Line Precharge (AUSP) technology will reduce the tPROG parameter by about 2%. A little more acceleration comes from reducing the capacitive load on the WL line, which will provide the programmable dummy string (PDS) method. The All Pass Rise (APR) method will result in a reduced read time (tR) and a 2% improvement in service during erasure.
A 3D NAND generation model is used to compile this image. Source: blocksandfiles.com
As mentioned previously, NAND 300+ memory will be released at the end of the year or even later in the first year of 2024, with all of the major players in the market establishing its speed.
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