SK hynix presented a 3D NAND flash memory with over 300 layers at the ISSCC 2023, which highlights the challenge of improving the technical processes for the manufacturing of multilayer flash memory: from 164 MB / s to 194 MB / s.
The previous record holder is a 238-layer 3D NAND SK hynix. Image source: SK hynix
SK hynix engineers are working on two main and most vital areas: increasing the recording density (reducing the cost of storing each bit of data) and improving performance. Both involve an increase in the resistance of the wordline (WL) line connecting the cells in the matrix row.
Comparison of 238 and 300-layer 3D NANDs
The following steps will be taken to speed up the writing, erasing, and reading process.
Instead of the previously double DPGM verification, it is proposed to use a three-step programming verification (TPGM) technique. Cell programming time will be reduced as a result of the TPGM technology.
The new Adaptive Unselected Line Precharge (AUSP) technique will reduce the tPROG parameter by about 2%. This will provide a little more power through the programmable dummy string (PDS) method. The All Pass Rise (APR) method will result in a 2% decrease in read time, resulting in a faster response time for the WL line to a new voltage level.
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As stated above, 1-Tbit 3D NAND TLC from SK hynix will be increased from 164 MB / s to 194 MB / s, with a simultaneous increase in recording density. NAND 300+ memory will be delivered by the end of this year or even before the beginning of 2024, all major players in the NAND memory market will develop it.
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